The 3-transistor dynamic cell, and semiconductor integrated circuits using it, are known for a long time. The 3-transistor dynamic cell has the advantages as follows: because the number of elements of the 3-transistor dynamic cell is smaller than that of a static cell that uses six transistors (hereinafter referred to as “6T cell”), the high density can be achieved; and in contrast to a 1-transistor dynamic cell (1T cell), the 3-transistor dynamic cell produces a gain at the time of reading, which enables high-speed operation.
As an example of documents about the 3-transistor cell (hereinafter referred to as “3T cell”), there is a patent document 1. This invention is intended to achieve the speedup of read operation by changing the potential of a source of a storage transistor Tr from 0 V to the minus potential at the time of reading a 3T cell.
In the meantime, what is disclosed in a patent document 2 is a transistor in which an extremely thin semiconductor is used for a channel and the leakage current is reduced by making use of a quantum mechanical confinement effect in a film thickness direction.
Patent document 1: Japanese Patent Laid-Open No. 2000-11642
Patent document 2: U.S. Pat. No. 6,576,943